Phase-locked loop systems are used in a variety of applications for synchronizing the phase of a local oscillator with the frequency of incoming signals, either analog or digital. Digitally controlled oscillators (DCO) are increasingly being used in phase-locked loop (PLL) systems for many applications. All digital phase-locked loops, however, generally do not provide the level of performance obtained from analog PLL systems. This is particularly true of digital phase-locked loop systems which are used to synchronize a digitally controlled oscillator (DCO) with the synchronization field frequency and the incoming data obtained from floppy disks used in personal computers and the like. The problem primarily is due to the granularity of digital systems (introducing quantization noise). Here, the penalty is offset by the use of "intelligent" filtering.
A problem, which is inherent in the data encoded in a floppy disk, is that at high density the data on a floppy disk (or on a computer hard disk) may suffer from bit shifting, that is, a tendency of bit pulses, which are close to one another, to appear to push apart, due to the algebraic addition or superposition of the waveforms. This occurs because these pulses are encoded as magnetic flux transitions on the disk, which tend to interfere with one another. If pulses properly appear in each bit position, there is no bit shift. This, however, is an ideal situation. Frequently pulses are missing or are shifted, which causes the synchronization of the oscillator in a digitally controlled phase-locked loop to be subject to loop "jitter" or hunting. The reason is that relatively large phase adjustments may be made by the PLL whenever errors due to bit shift occur; and these adjustments then need to be corrected when properly located data pulses occur.
A typical approach to deal with the problem noted above, for both analog and digital PLL's, is to make the filter in the PLL loop very low-pass or low-gain, that is, to make the gain and bandwidth of the filter such that the PLL cannot track the change in bit position if it is large. This approach, however, causes the initial locking to the incoming signal during synchronization to be slow. Consequently, the filter often is a compromise between the requirement for positive and quick locking and the desirability to prevent the filter from tracking changes in large bit position shifts.
Another approach is to employ a multi-section or multifunction filter, which is operated in a high-gain mode for synchronization and a low-gain mode for tracking. This, however, introduces increased complexity to systems in which it is used.
It is desirable to provide a filter for a digital PLL which always is operated in a high-gain mode of operation, and which, at the same time, is not subject to erroneous output as a result of bit shifting.